The present invention relates to a plural line buffer type memory LSI, and more specifically to a plural line buffer type memory LSI including a plurality of line buffers added to a memory section so as to be able to effectively reduce a memory access delay.
As a technology for elevating the performance of a memory LSI, attention has been focused on a plural line buffer type memory LSI. This plural line buffer type memory LSI is so configured that a plural line buffer section composed of a plurality of line buffers is provided adjacent to a memory section within a memory LSI, and a portion of data stored in the * memory section is prefetched in the plural line buffer section (data is previously read out). This plural line buffer type memory LSI is required to effectively reduce a delay time in a memory access, in order to realize a high speed access.
As a typical example of the above mentioned plural line buffer type memory LSI, a Virtual Channel Memory (VCM) architecture reported by NEC Corporation is already known. This VCM architecture is actually incorporated in a commercially available 128M-bit DRAM, and is disclosed in a 128M-bit Virtual Channel SDRAM Data Sheet available from NEC Corporation. FIG. 19 briefly illustrates a circuit block of the 128M-bit VC-SDRAM. This 128M-bit VC-SDRAM will be called a xe2x80x9cPrior Artxe2x80x9d 1 in this specification. In this Prior Art 1, a line buffer is called a channel. As well known, a memory section 107 in the DRAM is activated in units of page, and the activated page is read out to a sense amplifier part 112 within the memory section 107. In the case of a conventional DRAM (called a xe2x80x9cpage type memory LSIxe2x80x9d hereinafter), data is read out in units of word, from the activated page (read out to the sense amplifier part). (The page type memory LSI is exemplified by SDRAM, and its detail is disclosed in a 128M-bit SDRAM Data Sheet available from NEC Corporation.) Differently from this SDRAM, the VC-SDRAM of the Prior Art 1 is characterized in that data of a portion called a segment, in the activated page, is read and written at a time between the memory section and a plural line buffer section 108. In the Prior Art 1, here, the size of the page, the segment and the word are 8 kbits, 2 kbits and 16 bits, respectively, and the number of the line buffers is 16. FIG. 20 shows a truth table of commands used in the Prior Art 1. Here, a bank address, a row address, a segment address (indicating a segment within a page), a column address, and a line buffer number are 1 bit, 14 bits, 2 bits, 9 bits and 4 bits, respectively.
As shown in detail in FIGS. 19 and 20, the memory access in the Prior Art 1 is realized by two steps of a background operation and a foreground operation. The background operation is a processing required for a data transfer in units of segment, performed between the memory section 107 and the plural line buffer section 108. The foreground operation is a data transfer processing in units of word, performed between the plural line buffer section 108 and a data input/output terminal group of a data buffer. The background operation mainly includes four kinds of operation, which are a page open operation for activating a page to read out data to the sense amplifier part 112 (ACT instruction), a prefetch operation for reading a desired segment from the (activated) page read to the sense amplifier part 112 in tie memory section 107, to the plural line buffer section 108 (PFC instruction), a restore operation for writing back a segment into the (activated) page in tie memory section 107 read to the sense amplifier part 112 (RST instruction), and a page close operation for closing the activated page to be ready to activate another page (PRE instruction). On the other hand, the foreground operation mainly includes two kinds of operation, which are a buffer read operation for reading a word from a desired line buffer 115 within the plural line buffer section 108 (READ instruction) and a buffer write operation for writing a word into a desired line buffer 115 (WRITE instruction). In the Prior Art 1, incidentally, the plural line buffer section 108 are constituted to be full-associative. This means that it is possible to read out a segment at an arbitrary position to an arbitrary line buffer 115.
In the plural line buffer type memory LSI, since it is necessary to designate the line buffer 115, it is necessary to increase the number of input/output terminals or alternatively to use a plurality of commends, in comparison with the page type memory LSI which uses no line buffer 115. In order to ensure compatibility with input/output terminals of the page type memory LSI, the Prior Art 1 is so configured to designate the line buffer by use of the latter means. FIG. 21 illustrates a procedure for reading out the data from the memory section 107 to the data input/output terminals in the Prior Art 1. This procedure is carried out by the following three operations: (1) First, a page is designated by a bank address and a row address, and the designated page is activated and held by the sense amplifier part (ACT instruction). (2) Next, a segment is designated from the page held in the sense amplifier part, by the bank address and the row address, and the designated segment is written into the line buffer 115 designated by the line buffer number (PFC instruction). (3) Finally, the line buffer is designated by the line buffer number, and a word designated by a column address is read out from the designated line buffer (READ instruction).
In the page type memory LSI which uses no line buffer 115, since it is unnecessary to designate the line buffer, the PFC instruction is not necessary. Therefore, the plural line buffer type memory LSI has an increased delay time in a memory access in comparison with the page type memory LSI, since the commands have increased, in the case that there is a restriction in an interval for issuing the commands. In addition, as shown in FIG. 21, the Prior Art 1 is required to decode again the bank address already decoded by the ACT instruction when the PFC instruction is received, and similarly to decode again the line buffer address already decoded by the PFC instruction when the READ instruction is received. In the Prior Art 1, therefore, a reduplicate operation is necessary, so that the delay time in the memory access becomes large.
Therefore, the plural line buffer type memory LSI is desired to reduce the delay time in the memory access attributable to the restriction in connection with the issue of the commands, while maintaining the compatibility with the input/output terminals of the page type memory LSI and suppressing the increase in the number of input/output terminals.
Accordingly, it is an object of the present invention to provide a plural line buffer type memory LSI capable of reducing the delay time in the memory access attributable to the restriction in connection with the issue of the commands.
Another object of the present invention is to provide a plural line buffer type memory LSI capable of reducing the delay time in the memory access attributable to the restriction in connection with the issue of the commands, while maintaining the compatibility in input/output terminals or suppressing the increase in the number of input/output terminals.
The means for achieving the above objects can be defined as follows. Technical matters described in the following are suffixed with parenthesized reference numbers and signs. Those reference numbers and signs correspond to the reference numbers or signs given, to technical matters in at least one embodiment or a plurality of examples of a plurality of embodiments or examples of the present invention, in particular, technical matters shown in a drawing showing that embodiment or example. Those reference numbers and signs are given to clarify the correspondence between the technical matters defined in the claims and the technical matters of the embodiments and/or examples. However, this correspondence does not mean that the technical matters defined in the claims are interpreted to be limited to the technical matters of the embodiments and/or examples.
The plural line buffer type memory LSI in accordance with the present invention comprises a memory section (7), a plural line buffer section (8) having a plurality of line buffers (15) connected to the memory section (7), and a data buffer (9) connected to the plural line buffer section so that a data transfer is carried out between the memory section (7) and the plural line buffer section (8) and between the plural line buffer section (8) and the data buffer (9), and further includes a line selection register (16) for designating at least one line buffer (15) in the plural line buffer section (8). With addition of the line selection register (16), it is possible to reduce the delay in the memory access attributable to the restriction in connection with the issue of the commands.
As the result of the addition of the line selection register (16), the data transfer is carried out between the memory section (7) and the line buffer (15) designated by the line selection register (16). Furthermore, there is provided a data input/output terminal group connected to the data buffer (9), so that the data transfer is carried out between the line buffer (15) designated by the line selection register (16) and the data input/output terminal group (3).
When data is read out from a pre-activated memory section (7) to the data input/output terminal group (3), the data is written into the line buffer(s) (15) designated by the line selection register (16). Furthermore, a command input terminal group (2) and an address input terminal group (1) are provided, through which a bank address (designating one of a plurality of memory sections) and a row address (designating a page within a memory section) are supplied to the memory section (7), and an operation instruction is given for writing a page or a part of the page in the memory section (7) designated by the bank address and the row address, to the line buffer (15) designated by the line selection register (16). This operation instruction is given to an control circuit (6). Thus, it is possible to prevent an increase of the number of address input terminals, and to maintain compatibility with a general purpose memory LSI.
Through the command input terminal group (2) and the address input terminal group (1), the bank address and the row address are supplied to the memory section (7), and an operation instruction is given for writing data in the line buffer (15) designated by the line selection register (16), to a page or a part of the page in the memory section (7) designated by the bank address and the row address.
Through the command input terminal group (2) and the address input terminal group (1), a column address (designating a word in the line buffer) is inputted, and an operation instruction is given for outputting a word designated by the column address, in the data held in the line buffer (15) designated by and the line selection register (16), to the data input/output terminal group (3). Furthermore, through the command input terminal group (2) and the address input terminal group (1), a column address is inputted, and an operation instruction is given for writing data inputted through the data input/output terminal group (3), to a word designated by the column address, in the line buffer (15) designated by the line selection register (16). In addition, through the command input terminal group (2) and the address input terminal group (1), a bank address and a column address are inputted, and there are given an operation instruction for writing a page or a part of the page in the memory section (7) designated and pre-activated by the bank address, to the line buffer (15) designated by the line selection register (16), and another operation instruction for outputting a word designated by the column address, in the data held in the line buffer (15) designated by the line selection register (16), to the data input/output terminal group (3).
Through the command input terminal group (2) and the address input terminal group (1), a bank address and a column address are inputted, and there are given an operation instruction for writing a page or a part of the page in the memory section (7) designated and pre-activated by the bank address, to the line buffer (15) designated by the line selection register (16), and another operation instruction for writing the data inputted through the data input/output terminal group (3), into a word designated by the column address, to a word designated by the column address, in the line buffer (15) designated by the line selection register (16).
It is preferred that after completion of the operation of the instruction given as mentioned above, but prior to a next memory access operation, a pre-charging of the memory section (7) is automatically executed.
Furthermore, a plurality of line selection registers (16) are preferably provided. A portion of the address or the command for the memory access instruction is added with the number for designating one of the plurality of line selection registers (16), so that by using the line buffer (15) designated by the line selection register (16) designated by the added number, a data transfer is carried out between the memory section (7) and the plural line buffer section (8) and between the plural line buffer section (8) and the data input/output terminal group (3).
By using a portion of the address or the command for the memory access instruction, the line selection register (16) is designated, and the value written to the designated line selection register (16) is designated. After the memory access instruction is executed, the line selection register (16) is updated.
Furthermore, a control circuit (6) is added This control circuit (6) gives an operation instruction for designating one of the line selection registers (16) and changing the value of the designated line selection register.